Staff / Senior Staff Physical Design Engineer - India

• Bachelor’s/Master’s degree in Electrical Engineering or related field
• 8–12 years of experience in ASIC physical design
• Proven experience in full-chip or large block implementation and tapeouts
• Strong expertise in:
• Floorplanning and power planning
• Placement, CTS, routing, and physical verification
• Static Timing Analysis (STA) and timing closure
• Hands-on experience with industry-standard tools such as:
• Synopsys ICC2 / Cadence Innovus
• Synopsys PrimeTime
• Mentor Calibre
• Experience with advanced nodes (7nm and below preferred)
• Strong debugging and problem-solving skills
• Experience with low-power design techniques (UPF/CPF)
• Knowledge of EMIR analysis (e.g., Ansys RedHawk-SC)
• Familiarity with multi-voltage designs and power domains
• Experience with high-speed interfaces or complex SoCs (CPU/GPU/AI)
• Exposure to GLS and timing-related silicon debug
• Scripting expertise in Python/TCL

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.

Originally posted on Himalayas