Sr. Principal Product Engineer, Silicon Signoff Verification (SSV) / Digital Imp

• Advanced-node ASIC or SoC development
• Foundry qualification and certification programs
• Customer-facing product engineering
• Large-scale semiconductor design closure
• Timing, power, and SI signoff methodologies

Leadership Expectations

• Serve as technical lead for strategic customer engagements.
• Influence product roadmap and methodology direction.
• Mentor engineers and drive cross-functional collaboration.
• Lead technical reviews and customer escalation management.

Required Experience

• 8-12+ years of industry experience in semiconductor design, physical implementation, timing signoff, signoff methodology development, or product engineering.
• Strong experience supporting advanced-node SoC/ASIC designs through implementation, timing closure, ECO convergence, and tapeout.
• Proven experience working directly with semiconductor customers, R&D organizations, and field engineering teams to resolve complex technical challenges.
• Hands-on experience developing and deploying production signoff methodologies across multiple technology nodes and large-scale designs.
• Experience leading technical investigations, driving root-cause analysis, and influencing product enhancements for customer success.
• Demonstrated ability to independently own strategic customer engagements and drive cross-functional execution.
• Experience supporting advanced-node technologies (7nm, 5nm, 3nm, 2nm and beyond).
• Experience with large SoC designs (>100M instance designs) and hierarchical signoff methodologies.
• Experience with power-performance-area (PPA) optimization and signoff closure.
• Experience with customer-facing technical leadership across strategic semiconductor accounts.
• Experience in ECO closure methodologies, signal integrity analysis, glitch fixing, and timing correlation.
• Exposure to AI-assisted implementation and signoff workflows is highly desirable.
• Strong expertise in Static Timing Analysis (STA)
• Multi-mode multi-corner (MMMC) timing analysis
• Signoff methodologies and timing convergence
• Boundary model and hierarchical timing flows
• Physical implementation and signoff optimization
• Physical implementation and signoff environments